A pipelined divider with a small lookup table

Authors:
Chin-Long Wey;Shin-Yo Lin;Muh-Tian Shiue
Affiliations:
Department of Electrical Engineering, National Central University, Chung-Li, Taiwan;Department of Electrical Engineering, National Central University, Chung-Li, Taiwan;Department of Electrical Engineering, National Central University, Chung-Li, Taiwan
Venue:
IMCAS'07 Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Year:
2007

Citing 9
Cited 0

Residue number system arithmetic: modern applications in digital signal processing

Residue number system arithmetic: modern applications in digital signal processing
Computer arithmetic algorithms

Computer arithmetic algorithms
Fast Division Using Accurate Quotient Approximations to Reduce the Number of Iterations

IEEE Transactions on Computers - Special issue on computer arithmetic
Design Issues in Division and Other Floating-Point Operations

IEEE Transactions on Computers
Computer arithmetic: algorithms and hardware designs

Computer arithmetic: algorithms and hardware designs
Computer Arithmetic: Principles, Architecture and Design

Computer Arithmetic: Principles, Architecture and Design
Division and Square Root: Digit-Recurrence Algorithms and Implementations

Division and Square Root: Digit-Recurrence Algorithms and Implementations
A Cost-Effective Pipelined Divider with a Small Lookup Table

IEEE Transactions on Computers
Digit Selection for SRT Division and Square Root

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

The design of fast dividers is an important issue in high speed computing because division account for a significant fraction of the total arithmetic operation. Taylor series expansion is a well-known multiplicative scheme for high-performance division implementation. This study presents a simple architecture that implements a pipelined divider including the first 6 terms of the Taylor series expansion for approximation. Results show that the developed pipelined divider takes a lookup table of 32B for single precision with a latency of 8.90ns, and 56KB for double precision with 11.46ns, where the circuit is synthesized with TSMC 0.18µm digital CMOS standard cell library.