Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
Efficient implementation of a complex ±1 multiplier
Proceedings of the 12th ACM Great Lakes symposium on VLSI
A practical approach to the synthesis of arithmetic circuits using carry-save-adders
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
A complex ±1 multiplier is an integral element in modern CDMA communication systems, specifically as a pseudonoise code scrambler/descrambler. An efficient implementation is essential to reduce the critical path delay, power, and area of wireless receivers. A signed-binary architecture is proposed to achieve this complex multiplier function. Tradeoffs and design solutions are discussed. It is shown that the VLSI circuit implementation of the arithmetic operations may be significantly improved by using non-conventional number representations and transforming intermediate results from one format to another format. For a target function, the objective is to change the number representations of the input and output operands such that a minimum amount of logic circuitry is required to achieve a computation. An analytical framework is developed that expands the scope of the functions that can be efficiently implemented using signed-binary representation. Simulations exhibit a significant speed improvement as compared to alternative architectures.