Efficient implementation of a complex ±1 multiplier

Authors:
Boris D. Andreev;Eby G. Friedman;Edward L. Titlebaum
Affiliations:
University of Rochester, Rochester, NY;University of Rochester, Rochester, NY;University of Rochester, Rochester, NY
Venue:
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Year:
2002

Citing 2
Cited 1

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A practical approach to the synthesis of arithmetic circuits using carry-save-adders

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Complex ±1 Multiplier Based on Signed-Binary Transformations

Journal of VLSI Signal Processing Systems

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Abstract

A complex ±1 multiplier is an integral element in modern CDMA communication systems, specifically as a pseudonoise code scrambler/descrambler. Therefore, an efficient implementation is essential to reduce the critical path delay, power, and area of wireless receivers. A new architecture is proposed to achieve this complex multiplier function. Tradeoffs and design solutions as well as the interface with subsequent arithmetic circuits are discussed. Simulations exhibit a significant speed improvement as compared to alternative architectures. These results are also applicable to other arithmetic circuits.