Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression

Authors:
A. Masoudnia;H. Sarbazi-Azad;S. Boussakta
Affiliations:
School of Computer Science, Institute for Studies in Theoretical Physics and Mathematics (IPM), Tehran, Iran;School of Computer Science, Institute for Studies in Theoretical Physics and Mathematics (IPM), Tehran, Iran and Department of Computer Engineering, Sharif University of Technology, Tehran, Iran;School of Electronic and Electrical Engineering, The University of Leeds, Leeds, UK
Venue:
Computers and Electrical Engineering
Year:
2005

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Abstract

Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline architecture to compress and decompress images. The real filter calculation over 4x4 window blocks is done using a tree of carry save adders to ensure the high speed processing required for many applications. The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis reveals that the proposed architecture, implemented using current VLSI technologies, can process a video stream in real time.