Implementation of digital electronic arithmetic and its application

Authors:
Khader Mohammad;Sos Agaian;Fred Hudson
Affiliations:
Electrical and Computer Engineering Department, University of Texas at San Antonio, San Antonio, TX;Electrical and Computer Engineering Department, University of Texas at San Antonio, San Antonio, TX;Electrical and Computer Engineering Department, University of Texas at San Antonio, San Antonio, TX
Venue:
SMC'09 Proceedings of the 2009 IEEE international conference on Systems, Man and Cybernetics
Year:
2009

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Abstract

This Parameterized Digital Electronic Arithmetic (PDEA) model replaces linear operations with non-linear ones. In this paper we introduce a hardware implementation of the parametric image-processing framework that will accurately process images and speed up computation for addition, subtraction, and multiplication. Particularly, the paper presents the design of arithmetic circuits including parallel counters, adders and multipliers based in two high performance threshold logic gate implementations that we have developed. We will also explore new microprocessor architectures to take advantage of arithmetic. The experiments executed have shown that the algorithm provides faster and better enhancements from those described in the literature. Its potential applications include computer graphics, digital signal processing and other multimedia applications.