Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks

• Authors: Rohini Krishnan;O. P. Gangwal;Jos. v. Eijndhoven;Anshul Kumar
• Venue: VLSID '03 Proceedings of the 16th International Conference on VLSI Design
• Year: 2003

We present an innovative design of an accurate, 2D DCTIDCT processor, which handles scaled and sub-sampled inputblocks efficiently. In the IDCT mode, the latency of theprocessor scales with the size of the input blocks varyingfrom 7 cycles for an 1x1 block to 38 cycles for an 8x8 block.This scalability is possible because the processor has inputdata dependant control by which it can exploit the reducedcomputational needs of sub-sampled blocks and blocks ofsmaller sizes to work in lesser cycles. This is a very usefulfeature for MPEG and HDTV decoders and has hitherto notbeen exploited. Clocking at 150 Mhz, the processor satisfiesthe high sample rate requirement of dual MPEG stream HDdecoding with a picture size of 1920 x 1080 at 30 frames persecond. Fixed word length and accuracy simulations of ourdesign shows that it conforms to the accuracy specificationsof the CCITT standard within a 16 bit data path.A methodology based on architecture level synthesis isused to design the VLIW processor core. The VLIW designexploits the Instruction Level Parallelism present in theDCT/IDCT application, efficiently. The processor core ischaracterised by an area of 0.834 mm sq. and a frequencyof 150 Mhz in 0.18 micron CMOS technology.