VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications

Authors:
V. Srinivasan;K. J.R. Liu
Affiliations:
Crystal Semicond. Corp., Austin, TX;-
Venue:
IEEE Transactions on Circuits and Systems for Video Technology
Year:
1996

Citing 0
Cited 6

Mpeg2 Video Encoding in Consumer Electronics

Journal of VLSI Signal Processing Systems - Special issue on recent development in video: algorithms, implementation and applications
A Low Power 8 × 8 Direct 2-D DCT Chip Design

Journal of VLSI Signal Processing Systems
An Efficient Architecture for the In-Place Fast Cosine Transform

Journal of VLSI Signal Processing Systems
An efficient architecture for the in place fast cosine transform

ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks

VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Memory-Efficiency and high-speed architectures for forward and inverse DCT with multiplierless operation

PSIVT'06 Proceedings of the First Pacific Rim conference on Advances in Image and Video Technology

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we present a full-custom VLSI design of high-speed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been implemented to demonstrate its performance. We show that the VLSI implementation of this class of DCT/IDCT algorithms can easily meet the high-speed requirements of high-definition television (HDTV) due to its modularity, regularity, local connectivity, and scalability. Our design of the 8×8 DCT/IDCT can operate at 50 MHz (or have a 50 MSamples/s throughput) based on a very conservative estimate under 1.2 μ CMOS technology. In comparison to the existing designs, our approach offers many advantages that can be further explored for even higher performance