Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
MPEG: a video compression standard for multimedia applications
Communications of the ACM - Special issue on digital multimedia systems
DCT/IDCT processor for HDTV developed with DSP silicon computer
Journal of VLSI Signal Processing Systems - Special issue: video/image signal processing
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications
IEEE Transactions on Circuits and Systems for Video Technology
A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method
IEEE Transactions on Circuits and Systems for Video Technology
A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications
IEEE Transactions on Circuits and Systems for Video Technology
High throughput CORDIC-based systolic array design for the discrete cosine transform
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
VLSI implementation of a configurable IP Core for quantized discrete cosine and integer transforms
International Journal of Circuit Theory and Applications
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This paper presents the design and implementation of a low power 8 × 8 2-D DCT chip based on a computation-effective algorithm. Computational complexity can be reduced by simplifying the direct 2-D algorithm. Thus, the low power consumption is achieved due to complexity reduction. Besides, the parallel distributed-arithmetic (DA) technique is used to realize constant multiplication due to the low-power consideration. Additionally, the 2 V-power supply is practiced in circuit implementation for now and future battery operated applications. By using the TSMC 0.6 μm single-poly double-metal technology, 133 mW power consumption at 100 MHz and the 133 MHz maximum operation speed are achieved by critical path simulation.