A Low Power 8 × 8 Direct 2-D DCT Chip Design
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
An Efficient Architecture for the In-Place Fast Cosine Transform
Journal of VLSI Signal Processing Systems
An efficient architecture for the in place fast cosine transform
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
50 years of CORDIC: algorithms, architectures, and applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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We propose a modified fast algorithm for discrete cosine transform (DCT) by transferring the results from the discrete Hartley transform (DHT) to one additional CORDIC (coordinate rotation digital computer) computing stage. A fast CORDIC-based systolic array is designed with four derived attractive features, including: (1) the single/double data folding feature; (2) the constructive feature; (3) the to-computing feature; and (4) the redundant computation. Due to its properties, the proposed design has an efficient hardware utilization and a high throughput rate. By using the redundant path, this design also has the capability of error detection