Unified Architecture for Divide and Conquer Based Tridiagonal System Solvers
IEEE Transactions on Computers
An Adaptation of the Fast Fourier Transform for Parallel Processing
Journal of the ACM (JACM)
Parallel Architecture for Fast Transforms with Trigonometric Kernel
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Computers
An efficient CORDIC array structure for the implementation ofdiscrete cosine transform
IEEE Transactions on Signal Processing
VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications
IEEE Transactions on Circuits and Systems for Video Technology
A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications
IEEE Transactions on Circuits and Systems for Video Technology
High throughput CORDIC-based systolic array design for the discrete cosine transform
IEEE Transactions on Circuits and Systems for Video Technology
An Efficient Architecture for the In-Place Fast Cosine Transform
Journal of VLSI Signal Processing Systems
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The cosine transform (DCT) is in the core of image encoding and compression applications. We present a new architecture to efficiently compute the fast direct and inverse cosine transform which is based on reordering the butterflies after their computation. The designed architecture exploits locality, allowing pipelining between stages and saving memory (in place). The result is an efficient architecture for high speed computation of the DCT that reduces significantly the area required to VLSI implementation.