Solving tridiagonal systems on ensemble architectures
SIAM Journal on Scientific and Statistical Computing
Algorithms for special tridiagonal systems
SIAM Journal on Scientific and Statistical Computing
Efficient Tridiagonal Solvers on Multicomputers
IEEE Transactions on Computers
An Adaptation of the Fast Fourier Transform for Parallel Processing
Journal of the ACM (JACM)
An Efficient Parallel Algorithm for the Solution of a Tridiagonal Linear System of Equations
Journal of the ACM (JACM)
A VLSI Constant Geometry Architecture for the Fast Hartley and Fourier Transforms
IEEE Transactions on Parallel and Distributed Systems
FFTs on mesh connected computers
Parallel Computing
Mapping of Trellises Associated with General Encodersonto High-Performance VLSI Architectures
Journal of VLSI Signal Processing Systems
An Efficient Architecture for the In-Place Fast Cosine Transform
Journal of VLSI Signal Processing Systems
An efficient architecture for the in place fast cosine transform
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
A cost-optimal parallel implementation of a tridiagonal system solver using skeletons
Future Generation Computer Systems - Special issue: Parallel computing technologies
A cost-optimal parallel implementation of a tridiagonal system solver using skeletons
Future Generation Computer Systems - Special issue: Parallel computing technologies
| Hi-index | 14.98 |
The solution of tridiagonal systems is a topic of great interest in many areas of numerical analysis. Several algorithms have recently been proposed for solving triadiagonal systems based on the Divide and Conquer (DC) strategy. In this work we propose a unified parallel architecture for DC algorithms which present the data flows of the Successive Doubling, Recursive Doubling and Parallel Cyclic Reduction methods. The architecture is based in the perfect unshuffle permutation, which transforms these data flows into a constant geometry one. The partition of the data arises in a natural manner, giving way to a systolic data flow with a wired control section. We conclude that the constant geometry Cyclic Reduction architecture is the most appropriate one for solving tridiagonal systems and, from the point of view of integration in VLSI technology, is the one which uses the least amount of area and the smallest number of pins.