A Unified Approach to a Class of Data Movements on an Array Processor
IEEE Transactions on Computers
Unified Architecture for Divide and Conquer Based Tridiagonal System Solvers
IEEE Transactions on Computers
An Adaptation of the Fast Fourier Transform for Parallel Processing
Journal of the ACM (JACM)
Array Permutation by Index-Digit Permutation
Journal of the ACM (JACM)
Parallel Architecture for Fast Transforms with Trigonometric Kernel
IEEE Transactions on Parallel and Distributed Systems
An efficient architecture for the in place fast cosine transform
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
An efficient CORDIC array structure for the implementation ofdiscrete cosine transform
IEEE Transactions on Signal Processing
VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications
IEEE Transactions on Circuits and Systems for Video Technology
A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications
IEEE Transactions on Circuits and Systems for Video Technology
High throughput CORDIC-based systolic array design for the discrete cosine transform
IEEE Transactions on Circuits and Systems for Video Technology
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The two-dimensional discrete cosine transform (2D-DCT) is at the core of image encoding and compression applications. We present a new architecture for the 2D-DCT which is based on row-columndecomposition.An efficient architecture to compute the one-dimensional fast direct (1D-DCT)and inverse cosine (1D-IDCT) transforms, which is based in reordering the butterflies after their computation, is also discussed. The architectures designed exploit locality, allowing pipelining between stages and saving memory (in-place). The result is an efficient architecture for highspeed computation of the (1D, 2D)-DCT that significantly reduces the arearequired for VLSI implementation.