An efficient two-dimensional inverse discrete cosine transform algorithm for HDTV receivers
IEEE Transactions on Circuits and Systems for Video Technology
New systolic array implementation of the 2-D discrete cosine transform and its inverse
IEEE Transactions on Circuits and Systems for Video Technology
A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications
IEEE Transactions on Circuits and Systems for Video Technology
A parallel decoder of programmable Huffman codes
IEEE Transactions on Circuits and Systems for Video Technology
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A study of the MPEG-2 video decoding standard in Main Profile @ Main Level has beenperformed, comparing the different solutions existing for the VLSI implementation of the basic functions (Huffman decoding, IDCT...) included in the standard. Afterwards, a new dynamicallyconfigurable architecture is proposed for the memory manager, which is necessary to deal with the large data flow inside the decoder. It is aimed at interfacing the external memory, arbitrating the accessrequests coming from the different decoding units and allowing generic memory requests through the definition of virtual addresses. It is shown that, by means of a particular data organization, thecircuit requires an external memory, which is a 2-MB DRAM in fast page or EDO mode, accessible via a64-bit bus. The memory manager works at 27 MHz and allows a real-time decoding for MP @ ML bitstreams. It has been synthesized in a 0.8-μm two-metal CMOS technology and presents a total area of 5.4 mm2 for 6500 gates.