Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit
Journal of VLSI Signal Processing Systems
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Compressing MIPS code by multiple operand dependencies
ACM Transactions on Embedded Computing Systems (TECS)
Multiple-symbol parallel decoding for variable length codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Data-parallel finite-state machines
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
| Hi-index | 0.00 |
Huffman coding, a variable-length entropy coding scheme, is an integral component of international standards on image and video compression including high-definition television (HDTV). The high-bandwidth HDTV systems of data rate in excess of 100 Mpixels/s presents a challenge for designing a fast and economic circuit for intrinsically sequential Huffman decoding operations. This paper presents an algorithm and a circuit implementation for parallel decoding of programmable Huffman codes by using the numerical properties of Huffman codes. The 1.2 μm CMOS implementation for a single JPEG AC table of 256 codewords of up to 16-b codeword lengths is estimated to run at 10 MHz with a chip area of 11 mm2, decoding one codeword per cycle. The design can be pipelined to deliver a throughput of 80 MHz for decoding input streams of consecutive Huffman codes. Furthermore, our programmable scheme can be easily integrated into data paths of video processors to support different Huffman tables used in image/video applications