Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse
Journal of VLSI Signal Processing Systems
A novel linear array for discrete cosine transform
IMCAS'10 Proceedings of the 9th WSEAS international conference on Instrumentation, measurement, circuits and systems
A novel linear array for discrete cosine transform
WSEAS Transactions on Circuits and Systems
Low power hardware-based image compression solution for wireless camera sensor networks
Computer Standards & Interfaces
Energy-Efficient watermark algorithm based on pairing mechanism
KES'05 Proceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I
PSIVT'06 Proceedings of the First Pacific Rim conference on Advances in Image and Video Technology
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Low-power design is one of the most important challenges to maximize battery life in portable devices and to save the energy during system operation. In this paper, we propose a low-power DCT (discrete cosine transform) architecture using a modified multiplierless CORDIC (coordinate rotation digital computer) arithmetic. The switching power consumption is reduced during DCT: the proposed architecture does not perform arithmetic operations of unnecessary bits during the CORDlC calculations. The experiment results show that we can reduce up to 26.1% power dissipation without compromise of the final DCT results. Also, the speed of the proposed architecture is increased about 10%. The proposed low-power DCT architecture can be applied to consumer electronics and portable multimedia systems requiring high throughput and low-power.