Hardware architecture design of an H.264/AVC video codec
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computers
A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC
Journal of Signal Processing Systems
Image compression with variable block size segmentation
IEEE Transactions on Signal Processing
Low-complexity transform and quantization in H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
Variable block-size transforms for H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
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Recent video coding standards with hybrid structure adopt variable block-size processing techniques including variable block-size motion estimation and compensation, variable block-size intra prediction, and variable block-size transform. This paper gives analysis on the variable block-size techniques based on software simulations, and variable block-size transform is specially studied. As a result of the analysis, a generalized dual quad-tree based variable block-size coding (DQTC) structure is proposed. This structure also shows good flexibility and expansibility, in which the prediction block-size set and the transform block-size set can be configured according to requirements and the implementation complexity constraints. Simulation results show a considerable performance improvement for the proposed structure with low implementation complexity while the coding block-size sets and parameters are optimized.