IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC
Journal of Signal Processing Systems
Fast algorithm and low-cost hardware-sharing design of multiple integer transforms for VC-1
IEEE Transactions on Circuits and Systems II: Express Briefs
A low-cost very large scale integration architecture for multistandard inverse transform
IEEE Transactions on Circuits and Systems II: Express Briefs
High Performance, Low Complexity Video Coding and the Emerging HEVC Standard
IEEE Transactions on Circuits and Systems for Video Technology
Hi-index | 0.00 |
The paper presents a unified hybrid architecture to compute the 8 × 8 integer inverse discrete cosine transform (IDCT) of multiple modern video codecs--AVS, H.264/AVC, VC-1, and HEVC (under development). Based on the symmetric structure of the matrices and the similarity in matrix operation, we develop a generalized "decompose and share" algorithm to compute the 8 × 8 IDCT. The algorithm is later applied to four video standards. The hardware-share approach ensures the maximum circuit reuse during the computation. The architecture is designed with only adders and shifters to reduce the hardware cost significantly. The design is implemented on FPGA and later synthesized in CMOS 0.18 um technology. The results meet the requirements of advanced video coding applications.