Fast algorithm and low-cost hardware-sharing design of multiple integer transforms for VC-1

Authors:
Chih-Peng Fan;Guo-An Su
Affiliations:
Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan;Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2009

Citing 2
Cited 3

Implementations of Low-Cost Hardware Sharing Architectures for Fast 8 × 8 and 4 × 4 Integer Transforms in H.264/AVC

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Efficient fast 1-D 8 × 8 inverse integer transform for VC-1 application

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A low-cost very large scale integration architecture for multistandard inverse transform

IEEE Transactions on Circuits and Systems II: Express Briefs
Low cost design of a hybrid architecture of integer inverse DCT for H.264, VC-1, AVS, and HEVC

VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
Efficient hardware implementation of 8 × 8 integer cosine transforms for multiple video codecs

Journal of Real-Time Image Processing

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Abstract

In this brief, the fast 1-D multiple integer transforms of Windows Media Video 9 (WMV-9/VC-1) are proposed by matrix decompositions, additions, and row/column permutations. Then, the proposed fast 1-D integer transforms are hardware shared, and they can be applied to the 2-D transform scheme. The hardware costs of the proposed fast 1-D and 2-D integer transform designs are smaller than those of the previous individual designs without shares. With the hardware share, the proposed architecture is suitable for the low-cost implementation of the VC-1 codec.