A 2-D Forward/Inverse Integer Transform Processor of H.264 Based on Highly-parallel Architecture
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
Multiple-symbol parallel decoding for variable length codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Efficient Implementation of CAVLC for H.264/AVC
ICICIC '06 Proceedings of the First International Conference on Innovative Computing, Information and Control - Volume 3
High Performance VLSI Architecture Design for H.264 CAVLC Decoder
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder
IEEE Transactions on Multimedia
An efficient decoding of CAVLC in H.264/AVC video coding standard
IEEE Transactions on Consumer Electronics
Memory-efficient H.264/AVC CAVLC for fast decoding
IEEE Transactions on Consumer Electronics
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264
IEEE Transactions on Circuits and Systems for Video Technology
A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC
Journal of Signal Processing Systems
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In this paper, a combined kernel architecture for efficiently decoding the residual data in the H.264/AVC baseline decoder is proposed. The kernel architecture in the H.264/AVC decoder consists of context-based adaptive variable length code (CAVLC) decoder, inverse quantization (IQ), and inverse transforms (IT) units. Since the decoding speeds of these kernel units vary with data, traditional methods require data buffers between these units. The first proposed architecture efficiently combines CAVLC decoding and IQ procedures. The multiple 2-D transforms architecture is applied to all inverse transforms, including the 4 × 4 inverse integer transform, the 4 × 4 inverse Hadamard transform and the 2 × 2 inverse Hadamard transform, to attain fewer gate counts than those of existing transform designs. Simulation results show that the total number of gates is 14.1k and the maximum operating frequency is 130 MHz. For real-time requirements, in the worst case, the proposed architectures can achieve the operation speed of the H.264/AVC decoder up to 4VGA@30 frames/sec in 4:2:0 format.