A high performance and low power hardware architecture for the transform & quantization stages in H.264

Authors:
Muhsen Owaida;Maria Koziri;Ioannis Katsavounidis;George Stamoulis
Affiliations:
Department of Computer and Communication Engineering, University of Thessaly, Volos, Greece;Department of Computer and Communication Engineering, University of Thessaly, Volos, Greece;Department of Computer and Communication Engineering, University of Thessaly, Volos, Greece;Department of Computer and Communication Engineering, University of Thessaly, Volos, Greece
Venue:
ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
Year:
2009

Citing 1
Cited 1

H.264/AVC in wireless environments

IEEE Transactions on Circuits and Systems for Video Technology

A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC

Journal of Signal Processing Systems

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Abstract

In this work, we present a hardware architecture prototype for the various types of transforms and the accompanying quantization, supported in H.264 baseline profile video encoding standard. The proposed architecture achieves high performance and can satisfy Quad Full High Definition (QFHD) (3840×2160@150Hz) coding. The transforms are implemented using only add and shift operations, which reduces the computation overhead. A modification in the quantization equations representation is suggested to remove the absolute value and resign operation stages overhead. Additionally, a post-scale Hadamard transform computation is presented. The architecture can achieve a reduction of about 20% in power consumption, compared to existing implementations.