Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Efficient simulations among several models of parallel computers
SIAM Journal on Computing
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
The network architecture of the Connection Machine CM-5 (extended abstract)
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
An area-universal VLSI circuit
Proceedings of the 1993 symposium on Research on integrated systems
Randomized routing and sorting on fixed-connection networks
Journal of Algorithms
A lower bound for area-universal graphs
Information Processing Letters
The Fat-Pyramid and Universal Parallel Computation Independent of Wire Delay
IEEE Transactions on Computers
Deterministic on-line routing on area-universal networks
Journal of the ACM (JACM)
Time-Optimal Simulations of Networks by Universal Parallel Computers
STACS '89 Proceedings of the 6th Annual Symposium on Theoretical Aspects of Computer Science
An Area Lower Bound for a Class of Fat-Trees (Extended Abstract)
ESA '94 Proceedings of the Second Annual European Symposium on Algorithms
Universal emulations with sublogarithmic slowdown
SFCS '93 Proceedings of the 1993 IEEE 34th Annual Foundations of Computer Science
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An area-universal VLSI circuit can be programmed to emulate every circuit of a given area, but at the cost of lower area-time performance. In particular, if a circuit with area-time bounds (A,T) is emulated with a universal circuit with bounds (A_u,T_u), we say that the universal circuit has blowup A_u/A and slowdown T_u/T. A central question in VLSI theory is to investigate the inherent costs and tradeoffs of universal circuit designs.Prior to this paper, universal designs with O(1) blowup and O(log A) slowdown for area-A circuits were known. Universal designs for area-A circuits of O((A^((1/2)(1+epsilon)) log A) nodes, with O(A^epsilon) blowup and O(loglog A) slowdown, had also been developed. However, the existence of universal circuits with O(1) slowdown and relatively small blowup was an open question.In this paper, we settle this question by designing an area-universal circuit U^epsilon_A with O(1/epsilon) slowdown and O(epsilon^2 A^(epsilon) (log A)^4) blowup, for any value of the parameter epsilon, 1/log A