Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Unifying mesh- and tree-based programmable interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multilevel hierarchical interconnection structure for FPGA
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Efficient tiling patterns for reconfigurable gate arrays
Proceedings of the 2008 international workshop on System level interconnect prediction
The Y architecture for on-chip interconnect: analysis and methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This article presents the performance evaluation of two new diagonal routing tracks in FPGAs. We discuss the automatic detailed architecture generation issues and propose changes in the conventional placement and routing to suit these architectures better. We conduct a series of experiments on these architecture with MCNC Benchmarks, where key parameters are varied over practical ranges and we conclude that the results are well in accordance, as predicted by the theory.