The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Unifying mesh- and tree-based programmable interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new Multilevel Hierarchical MFPGA and its suitable configuration tools
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
The Y architecture for on-chip interconnect: analysis and methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagonal tracks in FPGAs: a performance evaluation
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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In this paper we present a few potentially efficient tiling patterns for gate-array realizations. We start with a brief recapitulation of tiling patterns, and fundamental limits of placement/routing in a two-dimensional plane. We state the first principles (i.e. Rent's Rule, Donath's result, equivalence of wire flux and wire length) and we proceed to define a method to mathematically evaluate tiling patterns basedon these principles. With this method we analyze a few regular tiling patterns and present a layout scheme for hexagonal and octagonal FPGAs. We briefly discuss the hierarchical gate array and we conclude with emphasis on the necessity of evolution of tiling patterns with the technology.