IEEE Transactions on Computers
A Survey of Multivalued Memories
IEEE Transactions on Computers
A Learning Multiple-Valued Logic Network: Algebra, Algorithm, and Applications
IEEE Transactions on Computers
Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Learning Multiple-Valued Logic Networks Based on Back Propagation
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
EMBRACE: emulating biologically-inspired architectures on hardware
NN'08 Proceedings of the 9th WSEAS International Conference on Neural Networks
Constraints in the design of CMOS MVL circuits
IMACS'08 Proceedings of the 7th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Using kolmogorov inspired gates for low power nanoelectronics
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
| Hi-index | 4.10 |
This tutorial places the developments and potential of multiple-valued signals and logic in the relevant context of binary and two-valued signals. It covers: the role of multivalued logic (MVL) in the binary world; multivalued representation; binary-related radices; multivalued functions; storage techniques in MVL; and implementation issues. An overview of applications is included.