Inter-neuron communication strategies for spiking neural networks

Authors:
F. Tuffy;L. J. McDaid;V. W. Kwan;J. Alderman;T. M. McGinnity;J. A. Santos;P. M. Kelly;H. Sayers
Affiliations:
Intelligent Systems Engineering Laboratory, Magee Campus, University of Ulster, Derry, Northern Ireland, BT48 7JL, UK;Intelligent Systems Engineering Laboratory, Magee Campus, University of Ulster, Derry, Northern Ireland, BT48 7JL, UK;Tyndall National Institute, Lee Maltings, Prospect Row, Cork, Ireland;Tyndall National Institute, Lee Maltings, Prospect Row, Cork, Ireland;Intelligent Systems Engineering Laboratory, Magee Campus, University of Ulster, Derry, Northern Ireland, BT48 7JL, UK;Intelligent Systems Engineering Laboratory, Magee Campus, University of Ulster, Derry, Northern Ireland, BT48 7JL, UK;Intelligent Systems Engineering Laboratory, Magee Campus, University of Ulster, Derry, Northern Ireland, BT48 7JL, UK;Intelligent Systems Engineering Laboratory, Magee Campus, University of Ulster, Derry, Northern Ireland, BT48 7JL, UK
Venue:
Neurocomputing
Year:
2007

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Abstract

This paper investigates alternative approaches to conventional metal interconnect for inter-neuron communication in spiking neural networks (SNNs). Two communication methodologies are considered where the first approach uses a time multiplexing architecture (TMA) where neurons on one layer are sampled sequentially and the associated spikes are transmitted to neurons in subsequent layers via a single metal track. Pulse transmission delays occur between neuron layers and the consequence of these delays on the performance of a SNN is investigated. In the second approach, capacitive coupling (CC) between neuron layers is used as the communication method and a model that predicts the dependency of the coupling signals between neuron layers as a function of the neuron density, frequency and track loading is presented. To maximise the available bandwidth and also the number of frequencies that can be utilised, micro-electro-mechanical systems (MEMS) are considered because of their high Q value. Issues such as frequency matching, MEMS processing, fabrication of capacitors and associated oscillator/filter circuits are discussed. The paper investigates both approaches and a comparison between the silicon area occupied by these and conventional metal is given for a 1.5@mm CMOS process.