Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Physical design with multiple on-chip voltages
Proceedings of the 2002 international symposium on Physical design
Multiple-Valued Logic its Status and its Future
IEEE Transactions on Computers
Design and analysis of a 32nm PVT tolerant CMOS SRAM cell for low leakage and high stability
Integration, the VLSI Journal
Carbon-nanotube-based voltage-mode multiple-valued logic design
IEEE Transactions on Nanotechnology
Modeling SWCNT Bandgap and Effective Mass Variation Using a Monte Carlo Approach
IEEE Transactions on Nanotechnology
CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
IEEE Transactions on Nanotechnology
Dramatically Low-Transistor-Count High-Speed Ternary Adders
ISMVL '13 Proceedings of the 2013 IEEE 43rd International Symposium on Multiple-Valued Logic
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Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New designs are simulated with HSPICE and 32nm CNTFET technology at various realistic conditions such as different power supplies, load capacitors, frequencies, and temperatures. Simulations results demonstrate their robustness and efficiency even in the presence of PVT variations. In addition, new noise injection circuits for ternary logic are also presented to perform noise immunity analysis.