Array-Based Analog Computation
IEEE Micro
A VLSI Implementation of an Analog Neural Network Suited for Genetic Algorithms
ICES '01 Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware
A VLSI Architecture for Weight Perturbation on Chip Learning Implementation
IJCNN '00 Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 4 - Volume 4
Low-power, high-performance analog neural branch prediction
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
A QoS network architecture to interconnect large-scale VLSI neural networks
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Interconnecting VLSI spiking neural networks using isochronous connections
IWANN'07 Proceedings of the 9th international work conference on Artificial neural networks
A convolutional neural network tolerant of synaptic faults for low-power analog hardware
ANNPR'06 Proceedings of the Second international conference on Artificial Neural Networks in Pattern Recognition
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A hardware neural network is presented that combines digital signalling with analog computing. This allows a high amount of parallelism in the synapse operation while maintaining signal integrity and high transmission speed throughout the system. The presented mixed-mode implementation achieves a synapse density of 4 k per mm2 in 0.35 μm CMOS. The current-mode operation of the analog core combined with differential neuron inputs reaches an analog precision sufficient for 10 bit parity while running at a speed of 0.8 Teraconnections per second.