Winner-take-all networks of O(N) complexity
Advances in neural information processing systems 1
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Low power, low voltage conductance-mode CMOS analog neuron
MICRONEURO '96 Proceedings of the 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems
Analog VLSI Implementation of Artificial Neural Networks with Supervised On-Chip Learning
Analog Integrated Circuits and Signal Processing
A VLSI Implementation of an Analog Neural Network Suited for Genetic Algorithms
ICES '01 Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware
Kerneltron: Support Vector `Machine' in Silicon
SVM '02 Proceedings of the First International Workshop on Pattern Recognition with Support Vector Machines
A Mixed-Mode Analog Neural Network Using Current-Steering Synapses
Analog Integrated Circuits and Signal Processing
Low-power, high-performance analog neural branch prediction
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
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The Neural Network Design Group at SGS-Thomson Microelectronics has been working to explore the advantages and limitations of analog computation and neural network architectures. We are investigating 3 large-scale analog VLSI chips, all of which work on problems in image processing. The use of analog computing arrays, because of their efficiency and regularity, have formed the basis of all of our designs, while several different computing modes, including current, charge, and conductance have been explored. Another area in which we have focused is on the use of floating-gate devices for both non-volatile analog storage and computation. This paper shares insights into the lessons we have learned, the results we have achieved and the limitations we have encountered. Particular emphasis is made on two subjects: computational efficiency and equivalent precision of array-based analog computing circuits.