New methods to color the vertices of a graph
Communications of the ACM
Computer Networks
ATM Input-Buffered Switches with the Guaranteed-Rate Property
ISCC '98 Proceedings of the Third IEEE Symposium on Computers & Communications
A Mixed-Mode Analog Neural Network Using Current-Steering Synapses
Analog Integrated Circuits and Signal Processing
IEEE Transactions on Neural Networks
A spiking neural network model of an actor-critic learning agent
Neural Computation
High-conductance states in a neuromorphic hardware system
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
A QoS network architecture to interconnect large-scale VLSI neural networks
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
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This paper presents a network architecture to interconnect mixed-signal VLSI integrate-and-fire neural networks in a way that the timing of the neural network data is preserved. The architecture uses isochronous connections to reserve network bandwidth and is optimized for the small data event packets that have to be exchanged in spiking hardware neural networks. End-to-end delay is reduced to the minimum by retaining 100% throughput. As buffering is avoided wherever possible, the resulting jitter is independent of the number of neural network chips used. This allows to experiment with neural networks of thousands of artificial neurons with a speedup of up to 105 compared to biology. Simulation results are presented. The work focuses on the interconnection of hardware neural networks. In addition to this, the proposed architecture is suitable for any application where bandwidth requirements are known and constant low delay is needed.