Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
An Analog VLSI System for Stereoscopic Vision
An Analog VLSI System for Stereoscopic Vision
Spiking Neuron Models: An Introduction
Spiking Neuron Models: An Introduction
A Review of the Integrate-and-fire Neuron Model: I. Homogeneous Synaptic Input
Biological Cybernetics
Network-on-Chip Architectures for Neural Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
NeuroNoC: neural network inspired runtime adaptation for an on-chip communication architecture
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Scalable network-on-chip architecture for configurable neural networks
Microprocessors & Microsystems
Scalable NoC-based architecture of neural coding for new efficient associative memories
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network
Neural Processing Letters
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A reconfigurable network architecture applied to spiking neural networks is presented. For hardware platforms for neural networks that implement some degree of realism of interest to neuroscientists, connectivity between neurons can be a major limitation. Recent data indicates that neurons in the brain form clusters of connections. Through the combination of this data and a routing scheme that uses a hybrid of short-range direct connectivity and an AER (Address Event Representation) network, the presented architecture aims to provide a useful amount of inter-neuron connectivity. A connection-centric design can provide opportunities for NoCs such as optimising power, bandwidth or introducing redundancy. A method of mapping a network to the architecture is discussed, along with results of optimal hardware specifications for a given set of network parameters.