Increasing the Capacity of a Hopfield Network without Sacrificing Functionality
ICANN '97 Proceedings of the 7th International Conference on Artificial Neural Networks
Connection-centric network for spiking neural networks
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Network-on-Chip Architectures for Neural Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
3D Integration for NoC-based SoC Architectures
3D Integration for NoC-based SoC Architectures
Sparse Neural Networks With Large Learning Diversity
IEEE Transactions on Neural Networks
| Hi-index | 0.00 |
We present the first NoC-based hardware implementation of Neural Coding (NC), which is a new approach that opens outstanding perspectives for the design of associative memories and learning machines. We first propose optimized architectures of memories and processing elements that allow for an efficient distributed implementation. Then we introduce different NoC architectures to interconnect all elements, it provides the required scalability and takes advantage of parallel transfer opportunities. Performance, cost and energy consumption tradeoffs of various NoC solutions are compared and discussed. Based on previous implementation results, we run SystemC-TLM that validate the behavior of the algorithm and of the efficiency of the dedicated architecture. This work demonstrates that this architecture can meet expected requirements in terms of scalability and hierarchy, and consequently that NC-based architectures are compliant with efficient hardware implementations of a new and promising model of associative memories.