Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
ROMM routing on mesh and torus networks
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Large Scale, Homogenous, Fully Distributed Parallel Machine, II
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
Proceedings of the 32nd annual international symposium on Computer Architecture
Improving routing efficiency for network-on-chip through contention-aware input selection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
ITNG '07 Proceedings of the International Conference on Information Technology
IEEE Transactions on Computers
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
IEEE Transactions on Computers
Performance evaluation of wireless networks on chip architectures
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A scalable micro wireless interconnect structure for CMPs
Proceedings of the 15th annual international conference on Mobile computing and networking
Hybrid wireless Network on Chip: a new paradigm in multi-core design
Proceedings of the 2nd International Workshop on Network on Chip Architectures
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Area and power-efficient innovative congestion-aware Network-on-Chip architecture
Journal of Systems Architecture: the EUROMICRO Journal
A Wireless Network-on-Chip Design for Multicore Platforms
PDP '11 Proceedings of the 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing
| Hi-index | 0.00 |
Integration of hundreds of processors on a chip will become practical thanks to ultra-deep submicron VLSI technology. As wiring delay becomes a bottleneck for a scalable design, on-chip interconnects turn into the critical issues for system performance and reliability. To mitigate long wiring delay impact, wireless on-chip communication infrastructures featuring hybrid mechanisms exploiting both wired and wireless communications have been proposed. By shortening long distance transmission latency and lowering wired network overhead, overall system transfer latency and energy dissipation are improved accordingly. However, unbalanced traffic management reduces the benefit of high speed wireless links so that wired networks also degrade accordingly. To extract the best performance for these hybrid networks, an intelligent congestion-aware router design is needed to balance traffic load and eliminate congestion delay. A sophisticated routing scheme accommodating more throughput and featuring light weight congestion-aware mechanism which uses the number of blocking buffers as a guideline to avoid serious congestion was designed and evaluated. Modified 7-port routers achieve better performance and the proposed routing algorithm successfully eliminates congestion scenarios and efficiently balances traffic loads. This is the first work to exchange congestion information locally and globally to improve network utilization and transmission quality. The experimental results showed significant improvement in transfer latency, network throughput and power efficiency with moderate hardware cost overhead.