Performance evaluation of wireless networks on chip architectures

Authors:
Amlan Ganguly;Kevin Chang;Partha Pratim Pande;Benjamin Belzer;Alireza Nojeh
Affiliations:
School of Electrical Engineering and Computer Science, Washington State University, Pullman, USA;School of Electrical Engineering and Computer Science, Washington State University, Pullman, USA;School of Electrical Engineering and Computer Science, Washington State University, Pullman, USA;School of Electrical Engineering and Computer Science, Washington State University, Pullman, USA;Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada
Venue:
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Year:
2009

Citing 0
Cited 3

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A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms

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Multi-hop communications on wireless network-on-chip using optimized phased-array antennas

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Abstract

The performance benefits of conventional Network-on-Chip (NoC) architectures are limited by the high latency and energy dissipation in long distance multihop communication between embedded cores. To alleviate these problems, wireless on-chip networks are envisioned. Using miniaturized on-chip antennas as an enabling technology, wireless NoCs (WiNoCs) can be designed. In this paper we elaborate on the design methodology and technology requirements for a WiNoC and evaluate its performance. It is demonstrated that a WiNoC outperforms its wireline counterpart in terms of network throughput and latency, and that energy dissipation improves by an order of magnitude.