Introduction to Evolutionary Computing
Introduction to Evolutionary Computing
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Exploring network topology evolution through evolutionary computations
Proceedings of the 8th annual conference on Genetic and evolutionary computation
Theoretical Computer Science
RF interconnects for communications on-chip
Proceedings of the 2008 international symposium on Physical design
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
IEEE Transactions on Computers
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
IEEE Transactions on Computers
NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication
HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
IEEE Transactions on Computers
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantitative theory of nanowire and nanotube antenna performance
IEEE Transactions on Nanotechnology
Performance Prediction of Carbon Nanotube Bundle Dipole Antennas
IEEE Transactions on Nanotechnology
High-throughput differentiated service provision router architecture for wireless network-on-chip
International Journal of High Performance Systems Architecture
A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms
Microprocessors & Microsystems
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The performance benefits of conventional Network-on-Chip (NoC) architectures are limited by the high latency and energy dissipation in long distance multihop communication between embedded cores. This limitation of conventional NoC architectures can be addressed by introducing long-range, high bandwidth and low power wireless links between the distant cores. Using miniaturized on-chip antennas as an enabling technology, wireless NoCs (WiNoCs) can be designed. In this paper, we elaborate the design principles of a hybrid WiNoC. It is demonstrated that a WiNoC outperforms its wireline counterpart and the performance gain is more significant for larger system size.