Application-aware deadlock-free oblivious routing
Proceedings of the 36th annual international symposium on Computer architecture
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Hybrid wireless Network on Chip: a new paradigm in multi-core design
Proceedings of the 2nd International Workshop on Network on Chip Architectures
An analysis of on-chip interconnection networks for large-scale chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Unconventional fabrics, architectures, and models for future multi-core systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Automation and Remote Control
Complex network inspired fault-tolerant NoC architectures with wireless links
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links
Proceedings of the great lakes symposium on VLSI
Performance evaluation and design trade-offs for wireless network-on-chip architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Distributed full switch as an ideal system area network for multiprocessor computers
Automation and Remote Control
Complex network-enabled robust wireless network-on-chip architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Extended block designs for ideal system area networks
Automation and Remote Control
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Current on-chip networks use a packet-switched design with a complex router at every hop, which imposes significant communication energy, delay, and throughput overhead. We propose reducing energy and delay, and increasing throughput, using express virtual channels. Packets traveling along these virtual express lanes, which connect distant nodes in the network, bypass intermediate routers, significantly reducing router overhead.