Communications of the ACM - Special section on computer architecture
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Multicomputer networks: message-based parallel processing
Multicomputer networks: message-based parallel processing
The iPSC/2 direct-connect communications technology
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
System design of the J-Machine
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Performance of multicomputer networks under Pin-out constraints
Journal of Parallel and Distributed Computing
An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-ary n-cubes
IEEE Transactions on Computers
A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
“Hypermeshes”: optical interconnection networks for parallel computing
Journal of Parallel and Distributed Computing
Alleviating channel bandwidth constraints in multicomputer networks
Journal of Systems Architecture: the EUROMICRO Journal
Analysis of fully adaptive wormhole routing in tori
Parallel Computing
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
The Impact of Pipelined Channels on k-ary n-Cube Networks
IEEE Transactions on Parallel and Distributed Systems
Architecture and Performance of the Hitachi SR2201 Massively Parallel Processor System
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
Graphs and Hypergraphs
Switch fabric architecture analysis for a scalable bi-directionally reconfigurable IP router
Journal of Systems Architecture: the EUROMICRO Journal
Switch fabric design for high performance IP routers: a survey
Journal of Systems Architecture: the EUROMICRO Journal
Modeling the effects of hot-spot traffic load on the performance of wormhole-switched hypermeshes
Computers and Electrical Engineering
An accurate performance model for network-on-chip and multicomputer interconnection networks
Journal of Parallel and Distributed Computing
Performance modeling of wormhole hypermeshes under hotspot traffic
CSR'07 Proceedings of the Second international conference on Computer Science: theory and applications
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Most existing multicomputers employ the torus topology along with deterministic routing to ensure simple router implementation, and thus fast communication. Efficient adaptive routing algorithms with minimum implementation requirements have recently been proposed to overcome the limitations of deterministic routing. Such algorithms have been incorporated in the latest generation of multicomputers, e.g. the Cray T3E, which are still based on low-dimensional k-ary n-cubes. Our previous studies have shown that a hypergraph network, referred to as the distributed crossbar switch hypermesh (DCSH), has several topological and performance advantages over traditional k-ary n-cubes when deterministic routing is used. This paper evaluates the relative merits of the DCSH and a variant of k-ary n-cubes, the torus, in the context of adaptive routing. The evaluation takes into account the effects of increased switching delays due to adaptivity, and implementation costs for various technologies (e.g. VLSI and multiple-chip technology). The results reveal that the DCSH is a potential alternative as a future high-performance multicomputer network, which can fully exploit the benefits of adaptive wormhole routing. Even though the torus has higher bandwidth channels than its DCSH counterpart, due to its simpler interconnect structure, adaptivity cannot reduce its higher message blocking delays inherent in its topology.