Gracefully Degradable Processor Arrays
IEEE Transactions on Computers
Warp architecture and implementation
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Fault-tolerant wafer-scale architectures for VLSI
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Algorithm transformations for parallel processing and vlsi architecture design
Algorithm transformations for parallel processing and vlsi architecture design
Concurrent Error Detection on Programmable Systolic Arrays
IEEE Transactions on Computers
A class of fault-tolerant systolic arrays for matrix multiplication
Mathematical and Computer Modelling: An International Journal
| Hi-index | 14.98 |
A linear systolic array with fault-tolerant capabilities is described. Fault tolerance is achieved by using triple time redundancy. The array is capable of undergoing reconfiguration and can operate in a gracefully degradable mode. The concept of algorithm remapping on degraded (smaller) arrays is integrated with that of graceful degradation to obtain a general fault-tolerance technique. A new technique for restructuring algorithms and executing them on a degraded array is discussed. The requisite modifications of the interconnection, switching, and control structures to achieve fault tolerance are discussed. Reliability analysis of the system is carried out, and the reliability is compared to that of nonredundant systolic arrays. Finally, the average performance of the system, with running time and throughput as performance metrics, is estimated.