Theory of linear and integer programming
Theory of linear and integer programming
Register allocation for software pipelined loops
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
Register requirements of pipelined processors
ICS '92 Proceedings of the 6th international conference on Supercomputing
Lifetime-sensitive modulo scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
A novel framework of register allocation for software pipelining
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Software pipelining with register allocation and spilling
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Decomposed software pipelining: a new perspective and a new approach
International Journal of Parallel Programming
Allocating registers in multiple instruction-issuing processors
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Minimizing register requirements of a modulo schedule via optimum stage scheduling
International Journal of Parallel Programming
Optimal software pipelining with function unit and register constraints
Optimal software pipelining with function unit and register constraints
On a graph-theoretical model for cyclic register allocation
Discrete Applied Mathematics
A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs
CC '92 Proceedings of the 4th International Conference on Compiler Construction
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Register saturation in instruction level parallelism
International Journal of Parallel Programming
Integrated Modulo Scheduling for Clustered VLIW Architectures
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Periodic register saturation in innermost loops
Parallel Computing
On minimizing register usage of linearly scheduled algorithms with uniform dependencies
Computer Languages, Systems and Structures
ACM Transactions on Embedded Computing Systems (TECS)
SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling
Journal of Combinatorial Optimization
Integrated Code Generation for Loops
ACM Transactions on Embedded Computing Systems (TECS)
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This article presents several theoretical and fundamentalresults on register need in periodic schedules, also knownas MAXLIVE. Our first contribution is a novel formula forcomputing the exact number of registers needed by a scheduledloop. This formula has two advantages: its computation can bedone using a polynomial algorithm with O(n lg n) complexity(n is the number of instructions in the loop), and it allows thegeneralization of a previous result [13]. Second, during softwarepipelining, we show that the minimal number of registers neededmay increase when incrementing the initiation interval (II),contrary to intuition. For the case of zero architectural delays inaccessing registers, we provide a sufficient condition for keepingthe minimal number of registers from increasing when incrementingthe II. Third, we prove an interesting property that enablesto optimally compute the minimal periodic register sufficiencyof a loop for all its valid periodic schedules, irrespective of II.Fourth and last, we prove that the problem of optimal stagescheduling under register constraints is polynomially solvablefor a subclass of data dependence graphs, while this problemis known to be NP-complete for arbitrary dependence graphs[7]. Our latter result generalizes a previous achievement [13]which addressed data dependence trees and forest of trees. Inthis study we consider cyclic data dependence graphs withouttaking into account any resource constraints. The aim of ourtheoretical results on periodic register need is to help currentand future software pipeliners achieve significant performanceimprovements by making better (if not best) use of the availableresources.