RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors
Proceedings of the ninth international symposium on Hardware/software codesign
Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems
Proceedings of the ninth international symposium on Hardware/software codesign
CALiBeR: a software pipelining algorithm for clustered embedded VLIW processors
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Design of Processor Arrays for Reconfigurable Architectures
The Journal of Supercomputing
On Periodic Register Need in Software Pipelining
IEEE Transactions on Computers
Efficient Method for Periodic Task Scheduling with Storage Requirement Minimization
COCOA 2008 Proceedings of the 2nd international conference on Combinatorial Optimization and Applications
Periodic register saturation in innermost loops
Parallel Computing
Early control of register pressure for software pipelined loops
CC'03 Proceedings of the 12th international conference on Compiler construction
SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling
Journal of Combinatorial Optimization
Integrated Code Generation for Loops
ACM Transactions on Embedded Computing Systems (TECS)
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