Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems

  • Authors:
  • Sid-Ahmed-Ali Touati

  • Affiliations:
  • INRIA. Domaine de Voluceau, BP 105, 78153 Le Chesnay cedex, France

  • Venue:
  • Proceedings of the ninth international symposium on Hardware/software codesign
  • Year:
  • 2001

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Abstract

To sustain the increases in processor performance, embedded and real-time systems need to find the best total schedule time when compiling their application. The optimal acyclic scheduling problem is a classical challenge which has been formulated using integer programming in lot of works. In this paper, we give a new formulation of acyclic instruction scheduling problem under registers and resources constraints in multiple instructions issuing processors with cache effects. Given a direct acyclic graph G = (V, E), the complexity of our integer linear programming model is bounded by &Ogr;(¦V¦2) variables and &Ogr;(¦E¦+¦V¦2) constraints. This complexity is better than the complexity of the existing techniques which includes a worst total schedule time factor.