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The Cydra 5 minisupercomputer: architecture and implementation
The Journal of Supercomputing - Special issue on instruction-level parallelism
The Journal of Supercomputing - Special issue on instruction-level parallelism
The complexity of simple computer architectures
The complexity of simple computer architectures
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Developing the AMD-K5 Architecture
IEEE Micro
The MIPS R10000 Superscalar Microprocessor
IEEE Micro
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
From algorithm parallelism to instruction-level parallelism: an encode-decode chain using prefix-sum
Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures
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The paper presents a novel static algorithm for mapping values to multiple register files. The algorithm is based on the edge-coloring of a bipartite graph. It allows the migration of values among the register files to keep the number of RAMs as small as possible.By comparison with the register file design used in the Cydra 5 mini-supercomputer, our approach substantially reduces the number of RAMs. This reduction actually grows with the issue rate. For a system with an issue rate of 6 instructions per cycle, the cost (gate count) of the register files are already cut by half. On a numerical workload, like the Livermore Loops, both designs achieve roughly the same performance.