The Cydra 5 minisupercomputer: architecture and implementation

Lifetime-sensitive modulo scheduling

PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation

Height reduction of control recurrences for ILP processors

MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture

Iterative modulo scheduling: an algorithm for software pipelining loops

MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture

Software pipelining

ACM Computing Surveys (CSUR)

Optimum modulo schedules for minimum register requirements

ICS '95 Proceedings of the 9th international conference on Supercomputing

Modulo scheduling with multiple initiation intervals

Proceedings of the 28th annual international symposium on Microarchitecture

Register allocation for predicated code

Proceedings of the 28th annual international symposium on Microarchitecture

Stage scheduling: a technique to reduce the register requirements of a modulo schedule

Proceedings of the 28th annual international symposium on Microarchitecture

A comparison of full and partial predicated execution support for ILP processors

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture

A reduced multipipeline machine description that preserves scheduling constraints

PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation

Instruction fetch mechanisms for VLIW architectures with compressed encodings

Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture

Dynamically scheduled VLIW processors

MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture

Predictability of load/store instruction latencies

MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture

From algorithm parallelism to instruction-level parallelism: an encode-decode chain using prefix-sum

Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures

Efficient formulation for optimal modulo schedulers

Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation

Scalable instruction-level parallelism through tree-instructions

ICS '97 Proceedings of the 11th international conference on Supercomputing

Compiler-controlled memory

Proceedings of the eighth international conference on Architectural support for programming languages and operating systems

Resource usage models for instruction scheduling: two new models and a classification

ICS '99 Proceedings of the 13th international conference on Supercomputing

Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Evaluating the Use of Register Queues in Software Pipelined Loops

IEEE Transactions on Computers - Special issue on the parallel architecture and compilation techniques conference

Modulo schedule buffers

Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture

EPIC: Explicitly Parallel Instruction Computing

Computer

Conflict-Free Access to Multiple Single-Ported Register Files

IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing

Reduced code size modulo scheduling in the absence of hardware support

Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture

Inlining of mathematical functions in HP-UX for Itanium® 2

Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization

Reducing code size in VLIW instruction scheduling

Journal of Embedded Computing - Low-power Embedded Systems

Compiling for reconfigurable computing: A survey

ACM Computing Surveys (CSUR)