Highly concurrent scalar processing
Highly concurrent scalar processing
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Register allocation for software pipelined loops
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Code generation schema for modulo scheduled loops
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Enhanced modulo scheduling for loops with conditional branches
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The Journal of Supercomputing - Special issue on instruction-level parallelism
Iterative modulo scheduling: an algorithm for software pipelining loops
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Modulo scheduling with multiple initiation intervals
Proceedings of the 28th annual international symposium on Microarchitecture
Analysis techniques for predicated code
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Software pipelining loops with conditional branches
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
A compilation technique for software pipelining of loops with conditional jumps
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
A comparative study of modulo scheduling techniques
ICS '02 Proceedings of the 16th international conference on Supercomputing
Conversion of control dependence to data dependence
POPL '83 Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Perfect Pipelining: A New Loop Parallelization Technique
ESOP '88 Proceedings of the 2nd European Symposium on Programming
Predicate-aware scheduling: a technique for reducing resource constraints
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Split-Path Enhanced Pipeline Scheduling
IEEE Transactions on Parallel and Distributed Systems
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Control and data dependence for program transformations.
Control and data dependence for program transformations.
Hardware/software mechanisms for increasing resource utilization on vliw/epic processors
Hardware/software mechanisms for increasing resource utilization on vliw/epic processors
The resource-constrained modulo scheduling problem: an experimental study
Computational Optimization and Applications
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Predicated execution enables the removal of branches by convertingsegments of branching code into sequences of conditional operations.An important side effect of this transformation is that thecompiler must unconditionally assign resources to predicated operations.However, a resource is only put to productive use whenthe predicate associated with an operation evaluates to True. To reducethis superfluous commitment of resources, we propose probabilisticpredicate-aware scheduling to assign multiple operationsto the same resource at the same time, thereby over-subscribing itsuse. Assignment is performed in a probabilistic manner using acombination of predicate profile information and predicate analysisaimed at maximizing the benefits of over-subscription in viewof the expected degree of conflict. Conflicts occur when two ormore operations assigned to the same resource have their predicatesevaluate to True. A predicate-aware VLIW processor pipeline detectssuch conflicts, recovers, and correctly executes the conflictingoperations. By increasing the effective throughput of a fixed setof resources, probabilistic predicate-aware scheduling provided anaverage of 20% performance gain in our evaluations on a 4-issueprocessor, and 8% gain on a 6-issue processor.