Maximal rate pipelined solutions to recurrence problems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
A compilation technique for software pipelining of loops with conditional jumps
ACM SIGMICRO Newsletter
The floating point performance of a superscalar SPARC processor
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Resource-Constrained Software Pipelining
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
A compilation technique for software pipelining of loops with conditional jumps
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
The Organization of Microprogram Stores
ACM Computing Surveys (CSUR)
A Fortran compiler for the FPS-164 scientific computer
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
A digital signal processor for real time generation of speech waveforms
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Programming a microcoded processor for speech waveform generation
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
Microprogramming: A Tutorial and Survey of Recent Developments
IEEE Transactions on Computers
A Hard Programmable Control Unit Design Using VLSI Technology
IEEE Transactions on Computers
Supporting RTL flow compatibility in a microarchitecture-level design framework
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Enforcing architectural contracts in high-level synthesis
Proceedings of the 48th Design Automation Conference
Design of a fast voxel processor for parallel volume visualization
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
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A pipelined processor is one whose computational capabilities are divided into several sequential stages, each of which may be working with an independent set of data at the same instant of time. Such processors are capable of handling large streams of data at very high rates. As with conventional CPUs, the microprogrammed control of such processors offers advantages not possible with hardwired controls. This paper discusses some unique tradeoffs that may be made in the design of microprogrammed pipelines. A sample pipeline demonstrates the characteristics of two extremes of microprogrammed control—one where the microinstruction specifies all activity in the pipeline at one instant of time (time-stationary) and one where the microinstruction “follows” the data through several clock periods (data-stationary). Several typical microprograms show the effects of these two variations on hardware costs, microprogrammability, and pipeline efficiency.