Numerical recipes: the art of scientific computing
Numerical recipes: the art of scientific computing
The microprogramming of pipelined processors
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
A high performance reconfigurable parallel processing architecture
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Automated interface code generation from Ada specifications
ACM SIGAda Ada Letters
Digital signal processors for computation intensive statistics and simulation
ACM SIGSIM Simulation Digest
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The WEDSP32C high-performance, programmable digital signal processor supports 32-bit floating-point arithmetic and is upwardly compatible with its predecessor, the WEDSP32. Because it is implemented in 0.75- mu m (effective channel length) CMOS technology, the second-generation device achieves high functional density with low power consumption. The DSP32C offers the following features: 25-Mflop operation; 16-Mb/s serial-input and serial-output ports; a 160-bit, parallel I/O port for control and data transfer; interrupt facilities; single-instruction mu -law and A-law data conversions; single-instruction conversions between integers and floating-point data; a byte-addressable, on-chip memory that is extendable off chip; direct memory access to and from internal and external memory via parallel and serial I/O ports; 16 Mbytes of address space; and IEEE Std. 754 floating-point format conversion. The authors describe the DSP32C's instruction set, architecture, and application development tools. The latter includes an assembler, a simulator, an optimizing C compiler, and special-purpose hardware.