Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
An analytical model for a class of processor-memory interconnection networks
IEEE Transactions on Computers
Classification Categories and Historical Development of Circuit Switching Topologies
ACM Computing Surveys (CSUR)
Switching strategies in a class of packet switching networks
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator network
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Building blocks for data flow prototypes
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Performance of a multiprocessor for Applicative programs
PERFORMANCE '80 Proceedings of the 1980 international symposium on Computer performance modelling, measurement and evaluation
Connection principles for multipath, packet switching networks
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
A Loop-Structured Switching Network
IEEE Transactions on Computers
Packet Switching Networks for Multiprocessors and Data Flow Computers
IEEE Transactions on Computers
An overview of the Texas reconfigurable array computer
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
Data structures for virtual-circuit implementation
Computer Communications
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This paper presents a formal scheme for addressing base and apex nodes in SW-banyan networks. This scheme is used for routing packets in the network. Packet-switching, in conjunction with the the circuit-switch mode of operation, offers a very flexible and powerful mechanism for interprocess communication in the multiprocessor architectures based on the banyan networks. Finally, a fault-tolerent scheme for re-routing the packets in the network is presented, in case the packet encounters a faulty node in its path.