A preliminary architecture for a basic data-flow processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
The NYU Ultracomputer—designing a MIMD, shared-memory parallel machine (Extended Abstract)
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Packet switching in banyan networks
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Packet communication in delta and related networks
Packet communication in delta and related networks
Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network
IEEE Transactions on Computers
Connection principles for multipath, packet switching networks
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Packet Switching Networks for Multiprocessors and Data Flow Computers
IEEE Transactions on Computers
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This paper investigates some methods for improving the performance of Single Stage Shuffle Exchange Networks (SENs) and Multistage Interconnection Networks (MINs). The three new switching strategies proposed use extra buffers to enhance performance. Approximate analysis and simulation results indicate significant improvement in performance for both SENs and MINs. An intuitive method for determining the applicability of the approximate analysis is discussed and some performance measures, which should be useful in evaluating the performance of networks are defined.