Configurable implementation of parallel memory based real-time video downscaler

Authors:
Eero Aho;Jarno Vanne;Timo D. Hämäläinen;Kimmo Kuusilinna
Affiliations:
Institute of Digital and Computer Systems, Tampere University of Technology, FI-33101 Tampere, Finland;Institute of Digital and Computer Systems, Tampere University of Technology, FI-33101 Tampere, Finland;Institute of Digital and Computer Systems, Tampere University of Technology, FI-33101 Tampere, Finland;Nokia Research Center, FI-33721 Tampere, Finland
Venue:
Microprocessors & Microsystems
Year:
2007

Citing 8
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Abstract

Image downscaling is necessary in multiresolution video streaming and when a camera captures larger resolution frames than required. This paper presents an implementation of a downscaler capable of real-time scaling of color video. The scaler can be configured to support nearly arbitrary scaling ratios. The scaling method is based on evenly divisible image sizes, which is, in practice, the case in most video and image standards. Bilinear interpolation is utilized as the scaling algorithm. Fine-grained parallel processing is utilized to increase performance and parallel memories are used to attain the required bandwidth. The results show that an FPGA implementation can downscale 16VGA and HDTV video in real-time with a complexity of less than half of the reference implementations.