An optimized linear skewing interleave scheme for on-chip multi-access memory systems
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Configurable implementation of parallel memory based real-time video downscaler
Microprocessors & Microsystems
Configurable data memory for multimedia processing
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Microprocessors & Microsystems
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This paper proposes an internal data memory architecture supporting byte and modulo addressing for processors having subword parallel processing capability, or alternatively, multiple SIMD-connected processing elements on-chip. Byte-addressable memory efficiently relieves the data word alignment problem in motion estimation block matching. In addition, a special modulo addressing allows part of the bytes in a word to be accessed simultaneously from the both ends of a circular buffer. With the modulo-addressable memory, the external memory bandwidth can be significantly reduced, while preserving efficient memory access performance in block-matching operations. The proposed data memory architecture consists of parallel memory modules, address computation circuitry, and data permutation network. Designs for different data bus widths (N= 2, 4, 8 bytes) are considered.