Theoretical limitations on the use of parallel memories.
Theoretical limitations on the use of parallel memories.
Interconnections for Parallel Memories to Unscramble p-Ordered Vectors
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
The Organization and Use of Parallel Memories
IEEE Transactions on Computers
On Linear Skewing Schemes and d-Ordered Vectors
IEEE Transactions on Computers
Vector access performance in parallel memories using skewed storage scheme
IEEE Transactions on Computers
Discrete Optimization Problem in Local Networks and Data Alignment
IEEE Transactions on Computers
Mappings for Conflict-Free Access of Paths in Elementary Data Structures
COCOON '00 Proceedings of the 6th Annual International Conference on Computing and Combinatorics
Microprocessors & Microsystems
On the L(h, k)-labeling of co-comparability graphs
ESCAPE'07 Proceedings of the First international conference on Combinatorics, Algorithms, Probabilistic and Experimental Methodologies
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The effective utilization of single-instruction-multiple-data stream machines depends heavily on being able to arrange the data elements of arrays in parallel memory modules so that memory conflicts are avoided when the data are fetched. Several classes of storage algorithms are presented. Necessary and sufficient conditions are derived which can be used to determine if all conflict can be avoided. For the matrix subparts most often demanded in numerical analysis computations, whenever the class of storage algorithms called periodic skewing schemes provides conflict-free access, the subclass called linear skewing schemes also provides such access.